SD Sniffer part 2

I've finally had time to play around a bit more with the SD sniffer I designed a few weeks ago.  I started placing all the active components on the board and also got to curse myself for choosing the tiny, tiny, SC70 packages for the comparators.  The SC70 package is tiny and the components  were quite tricky to solder, mostly because I don't have access to a stereo microscope any more.  But it all worked out in the end.

Since I have used the OpalKelly FPGA board before and have a lot of existing code for it, it didn't take long to hack together an FPGA image that could control the D/A converter on the board to set the reference voltage for the comparators.  With that done it was possible to probe the outputs from the comparators with a scope and see that the signals matched the signals on the SD bus.  One of the purposes with this board was to not put too much load on the SD data lines, and this actually seems to work.  I have a high speed SD card which runs at 48MHz which gets a lot of errors if I probe the CLK line with a normal 10x scope probe.  With the sniffer board it works fine at 48MHz without any errors.

A little while later I could actually get the signals into the FPGA and then stream them onto my PC.  The current FPGA image is rather simple, on every SD CLK edge it samples the SD CMD and SD DATA lines and stores them in a FIFO buffer inside the FPGA.  The Cypress FX2 USB controller on the OpalKelly board then streams the data from the FIFO to the PC.   This is basically what the USBee does, so this has the same limitation of 30MHz clock speed on the bus.  So the only advantage so far is that my SD sniffer doesn't affect the SD bus signals as much as the USBee does.

But since I have access to the FPGA on the OpalKelly board there's a lot more that can be done.  The USBee wastes a fair bit of the USB bandwidth since it always transfers 8 bits to the host for each sample.  The SD bus only uses 5 bits per sample, the CMD line and four DATA lines, so 3 out of every 8 bits going over the USB bus are unused.  With the FPGA it's quite simple to pack eight 5 bit samples into five 8 bit words.  So to be able to handle a 50MHz bus it needs 50*5/8 = 31.25MBit/s throughput on the USB bus which is just about what's possible.

But first I'll clean up the existing code a bit and then start working on some way of processing and presenting the raw SD bus data.

SD Sniffer

I need to debug a problem with a SD bus.  I have previously used a USBee SX with a custom firmware to sniff the bus and save a trace of all the SD signals to the hard drive so I could analyse them offline.  This works fine up to about 30MHz but then the USBee runs out of bandwidth to the host PC.  But the SD standard version 2 allows the bus to run at up to 50MHz and also tightens the electrical requirements for the SD bus, limiting impedance and capacitance so that the bus reliably can run at such high speeds.  So for modern cards the USBee can't keep up and the long wires to the USBee can introduce a bit too much loading and deteriorate the signals so much that the SD card will no longer work.

So I decided to build an adapter card which has a bunch of high impedance comparators sitting very close to the SD bus wires so that I can sniff the bus while changing the signals as little as possible.  The signals will then be fed into an OpalKelly XEM3001 FPGA Board that I happen to have lying around.  Anyway, since I have lost the source code that I used before to do the sniffing and analysis I have to rewrite everything anyway, so why not get a bit overambitious, I mean, what's the fun in doing the same thing over again?

Time to fire up Eagle and throw together some schematics.  The SD bus is available on a pin header on the board I'm debugging so I'm using the same pin header on my board.  Then I've put a SD card holder on the PCB so that I can plug a normal SD card into it.  Then there are a bunch of comparators, one for each signal on the SD bus, and then a D/A converter which gives the comparators a reference voltage to compare the SD signals with.  The outputs from the comparators go to a another pin header which matches the ZBUS connector on the OpalKelly board.  The comparators and the D/A are powered from the OpalKelly board.

 

Next the PCB design.  It did take quite a bit of time to squeeze everything onto a 2 layer board, but hopefully it'll all work.

Some of the symbols and footprints I'm using are from the SparkFun Eagle library.  I found the SD connector footprint on some forum on the net that I can't manage to find again.

I then mailed off the gerber files to a PCB manufacturer and settled down to wait.  14 days later the finished PCBs arrived in the mail.

This is the first time I've used iteadstudio.com and the results look quite good, so I'll definitely be using them again.

So the first thing I did was to solder the pin header and SD holder in place, and then put a SD card in the SD holder and plug the board into the SD bus, this way I could verify that the board would work as a plain SD extender:

And it did!  At least with an old an slow SD card.

So next up, test this with a modern high speed SD card running at 50MHz.  And after that, start soldering some active components onto the board.

This post is continued in part 2.